Circuits and Methods for Characterizing Random Variations in Device Characteristics in Semiconductor Integrated Circuits

ABSTRACT

Circuits for measuring and characterizing random variations in device characteristics of integrated circuit devices.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Divisional Application of U.S. application Ser.No. 10/643,193, filed on Aug. 18, 2003, the disclosure of which isherein incorporated by reference in its entirety.

TECHNICAL FIELD

The present invention relates generally to circuits and methods formeasuring and characterizing random variations in device characteristicsin semiconductor devices. The present invention further relates tocircuits and methods for measuring and characterizing device mismatch ofsemiconductor transistors due to local variations in devicecharacteristics resulting from random sources, and in particular, Vt(threshold voltage) variations between neighboring MOSFETs (Metal OxideSemiconductor Field Effect Transistors) of SRAM (Static Random AccessMemory) cells or other logic devices.

BACKGROUND

In the design of semiconductor integrated circuits, it is very importantto consider variations in device characteristics (device mismatch) suchas Vt (threshold voltage) for a given circuit design, in order toachieve circuit robustness and obtain high manufacturing functionalyields for such devices.

In general, variations in device characteristics include “systematic”variations and “random” variations. Systematic variations (or processvariations) are variations in a manufacturing process that equallyaffect some or all N-doped or P-doped elements of a local circuitdepending on, e.g., the orientation, geometry and/or location of adevice. For example, when manufacturing a semiconductor chip, systematicvariations in device characteristics can result from variations in maskdimensions (which causes geometry variations), variations in materialproperties of wafers, resists, etc., variations in the manufacturingequipment and environment (e.g., lens aberrations, flow turbulence, oventemperature, etc.) and variations in process settings (implant dose,diffusion time, focus, exposure energy, etc.). Systematic variationstypically have significant spatial correlations, i.e., circuits/devicesthat are near each other can be expected to have the same/similar amountof variations due to systematic sources of variation.

Given the high spatial correlation for systematic variations in devicecharacteristics between local devices, body biasing methods forcompensating/mitigating the sensitivity of circuit performance due tosuch systematic variations are well known and can be readily applied.

In contrast, random variations in device characteristics between devicesof a circuit, wafer, chip or lot, are uncorrelated. Random sources ofvariations, which cause device mismatch between neighboring devices in acircuit, can adversely affect circuit behavior even more drasticallythat systematic variations in circuits such as SRAM cells and senseamplifiers. Indeed, since systematic sources of variation equally affectneighboring devices, device mismatch between neighboring devices as aresult of systematic sources is negligible as compared to devicemismatch due to random sources of device characteristic variation. Thus,random variations in device characteristics (device mismatch) causesignificantly more deviation especially in circuit performance of theabove mentioned circuits, than systematic variations. Since randomvariations in device characteristics are uncorrelated, methods forcharacterizing or modeling such random variations are difficult andinaccurate. Providing the necessary “fixes” at the device and circuitlevels so as to limit the adverse effects of such random variations oncircuit performance, are expansive by way of silicon area consumed ascompared to those for systematic variations.

Although device mismatch may be caused by any number of variations indevice characteristics, random variations in Vt (threshold voltage)mismatch have significant impact on circuit performance for varioustypes of MOS circuits. In MOSFET devices, for example, random variationsin Vt between neighboring transistors are due primarily to fluctuationsin number and position of dopant atoms, but other sources include, forexample, randomness in line edge roughness of devices. Variations in Vtmismatch of MOSFETs of an SRAM cell can significantly degrade cellstability as is understood by those of ordinary skill in the art.Furthermore, Vt mismatches of transistors of a sense amplifier canadversely impact the offset voltage. In particular, because a senseamplifier senses a differential voltage applied at the gates of twoneighboring sensing devices (transistors), if there is a Vt mismatchbetween such devices, the mismatch adds to the voltage that the senseamplifier must counter before it can amplify the desired signal. By wayof further example, Vt mismatches can affect the performance of CMOSinverters, e.g., a Vt mismatch can cause variations in the trip voltage,that is, the point at which the output of the inverter switches betweenlogic states “1” and “0”.

As semiconductor integrated circuits become more highly integrated withsub-micron features sizes of MOS devices, and as power supply voltagesare reduced (for low power applications), the adverse effects of circuitperformance due to random variations in device mismatch are enhancedbecause such variations do not scale down with feature size and/orsupply voltage.

Accordingly, in order to provide robust circuit designs and enhancefunctional yield for a given process, circuit designers will try toaccurately assess/characterize the random contributions of devicemismatch, such as Vt mismatch, for example, that results from a givenfabrication process so as to determine the effects of such randomvariations on circuit performance.

Various simulations and experimental methods have been proposed anddeveloped for characterizing variations in device characteristics todetermine the effect of device mismatch in integrated circuit design. Ingeneral, such methods are based on statistical analysis or statisticalmodeling of device mismatches and performance differences that resultfrom device mismatch. Statistical design methods enable a circuitdesigner to determine the quantitative effect of device mismatch.

For instance, CAD (computer-aided design) tools and applications havebeen developed for statistical circuit design and performing statisticalsimulations using Monte

Carlo analysis. Monte Carlo simulation requires construction of astatistical model of device mismatch, for example, which model is usedfor simulating device mismatch. In general, with Monte Carlo analysis,parameter distributions (e.g., Normal/Gaussian) are assigned to desiredmodel parameters and then Monte Carlo simulations are performed usingsuch parameter distributions.

There are various disadvantages associated with methods such as MonteCarlo simulations. For instance, the characterization accuracy of suchmethods are limited based on the accuracy of the model that is employed.Moreover, such simulations typically do not capture all the sources ofVt mismatch. Moreover, Monte Carlo simulations are expensive in terms oftime and effort to develop.

Experimental techniques for characterizing device mismatch includeperforming statistical analysis on actual test data that is measuredfrom test structures. For example, FIG. 1 is a diagram that illustratesa conventional test circuit and method for characterizing devicemismatch. The test circuit of FIG. 1 comprises an array of NFETs orPFETs, wherein all the source terminals of the transistors in the arrayare commonly connected to terminal “S”. The gate terminals of thetransistors in a given column of the array (10) are commonly connectedto a Gi (e.g., i=1, . . . , 256) terminal, and the drain terminals ofthe transistors in a given row of the array (10) are commonly connectedto a Di (e.g., i=1, . . . , 32) terminal. A counter and decoder circuit(11) is responsive to a clock CLK signal for generating output signalsto sequentially activate one of the Gi terminals.

With the circuit of FIG. 1, test data is collected by selectivelyactivating the transistors, one at a time, in a given sequence, tomeasure the drain current ID vs. gate voltage VG (I-V) characteristicsfor each transistor in the array (10). For example, transistor T1 in thearray (10) is activated by applying Vdd to terminals G1 and D1, and thenthe current flowing in terminal S would be measured to obtain the I-Vcharacteristics of T1. Then, sequential activation of the terminals Giand Di would continue until each device in the array is measured. Forinstance, D1 would be maintained at Vdd while each Gi terminal would besequentially activated under control of the counter (11) to obtain theI-V characteristics in the first row of the array (10), and this processwould be repeated by sequentially activating G1-Gi for each activatedrow Di.

After the I-V measurements are collected for all the transistors in thearray (10) and stored in a database, the data can be retrieved andprocessed to extract various parameters such a Vt, transconductance,drain currents, etc. and generate distributions for such parameters. Inaddition, the Vt of neighboring devices in the array could be comparedto generate a distribution of the Vt mismatch between neighboringdevices. Assuming that the transistors in the array are the same (e.g.,the same channel lengths and widths), the measured distributions can beused to characterize device mismatch between the same or similartransistors to be included in a desired circuit design.

Although techniques which characterize device mismatch based on actualtest data measured using test structures (such as in FIG. 1) caneffectively determine parameter mismatch variance to some degree,uncertainty can be included in the test data as a result of variationsfrom sources from other than the MOSFET being characterized, whichresult from the testing procedure and/or testing circuit architecture,can reduce the accuracy of device mismatch analysis. For example, in thetest circuit of FIG. 1, test data that is measured for a giventransistor includes uncertainty resulting from gate leakage andsubthreshold leakage from unselected devices in the activated row andcolumn.

More specifically, by way of example, when terminals G1 and D1 areactivated (at Vdd) to collect data for transistor T1, the unselectedtransistors (T2 . . . T3) in the row D1 drive subthreshold leakagecurrents (current that flows from the drain to source terminal when gatevoltage is below the threshold voltage), which contribute to variationsin the drain current Id of transistor T1 that is being measured interminal S. Furthermore, the unselected transistors (e.g., T4, T5) incolumn G1 drive gate leakage current (leakage through gate oxide fromgate terminal to source terminal), which further adds to theuncertainties of the test data being measured for T1.

With the test structure of FIG. 1, other sources of variation that canadd to the uncertainty include systematic (process) variations thatexist when the array is too large. For instance, when the array is toolarge, variations in channel length of transistors in the array (10) mayoccur due to process variations, which contribute to parametervariations (e.g., Vt) in devices across the array (10).

Moreover, when the array is too large, the increase in temperature ofthe devices in the array during testing of transistors can add to theuncertainty of measured Vt, which is exponentially dependent ontemperature.

Accordingly, when attempting to characterize device mismatch due torandom sources, the sources of uncertainty, which result from thetesting circuit and/or methodology, can contribute to the variance ofthe test data. As such, device mismatch due to random Vt fluctuationscannot be accurately characterized and is overestimated. This is notdesirable since, as noted above, accurate characterization of randomvariation of device mismatch (e.g., Vt mismatch) between neighboringdevices is important for circuit analysis due to the significantlyadverse effects such random mismatches can have on circuit performance,functionality and yield.

Thus, it is highly desirable to develop circuits and methods that allowrandom Vt variations in device characteristics to be accurately andefficiently characterized for purposes of integrated circuit design.

BRIEF SUMMARY

The present invention is directed to circuits and methods for measuringand characterizing random variations in device characteristics ofsemiconductor integrated circuit devices. More specifically, circuitsand methods according to embodiments of the invention enable circuitdesigners to accurately measure and characterize random variations indevice characteristics (such as transistor threshold voltage (Vt))resulting from random placement of dopant atoms or line edge roughness,for purposes of integrated circuit design. Methods and circuitsaccording to embodiments of the invention are preferably implemented fordetermining variations in Vt mismatch between neighboring MOSFETs of agiven circuit being analyzed/designed, such as SRAM cells or other logicdevices, and using the determined variations in Vt mismatch tocharacterize random variations of the given circuit. Preferably,circuits and methods according to the present invention forcharacterizing device mismatch between transistors preferably measuresubthreshold DC voltage characteristics (VC) of pairs of devices (i.e.,gate voltage is below Vt), which eliminates uncertainty that arises fromgate leakage through unselected devices.

In one embodiment of the invention, method for characterizing randomvariations in device mismatch (e.g., Vt mismatch) between neighboringdevices comprises the steps of obtaining subthreshold DC voltagecharacteristic data (Vout vs. Vin) for a plurality of device pairs ofthe neighboring devices, analyzing such data to determine a distributionof Vin for a given Vout, and obtaining a distribution for Vt mismatchbased on the distribution of Vin. A distribution in Vt mismatch for apair of transistors, for example, can be directly measured usingsubthreshold DC voltage characteristic data that is obtained frommultiple pairs of such neighboring devices.

In another embodiment of the invention, a method for characterizingdevice mismatch in a semiconductor integrated circuit comprises:obtaining DC voltage characteristic data for one or more selected devicepairs of an integrated circuit, wherein the device pairs comprise pairsof neighboring transistors in the integrated circuit; determining adistribution of Vt (threshold voltage) mismatch for a selected devicepair using corresponding DC voltage characteristic data for the devicepair; determining a Vt variation of transistors in the integratedcircuit using one or more determined distributions of Vt mismatch forselected device pairs; and characterizing random variations of theintegrated circuit using one or more determined Vt variations oftransistors of the integrated circuit. Preferably, the step of obtainingDC voltage characteristic data for a selected device pair of anintegrated circuit comprises obtaining subthreshold DC voltagecharacteristic data while biasing the transistors of the device pair ina subthreshold region.

These and other exemplary embodiments, aspects, features, and advantagesof the present invention will become apparent from the followingdetailed description of the preferred embodiments, which is to be readin connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a diagram that illustrates a conventional test circuit that isused for measuring device parameters for characterizing device mismatch.

FIG. 2 is an exemplary circuit diagram that can be used forcharacterizing random device mismatches between a pair of transistors,according to an embodiment of the invention.

FIG. 3 is an exemplary circuit diagram that can be used forcharacterizing random device mismatches between a pair of transistors,according to another embodiment of the invention.

FIG. 4 is an exemplary circuit diagram that can be used forcharacterizing random device mismatches between a pair of transistors,according to another embodiment of the invention.

FIG. 5 a is an exemplary model according to an embodiment of theinvention for characterizing device mismatch using the circuit of FIG.2.

FIG. 5 b is an exemplary graphical diagram illustrating subthreshold DCvoltage characteristics that were measured for a plurality of circuitsas depicted in FIG. 2.

FIG. 6 is an exemplary model according to an embodiment of the inventionfor characterizing device mismatch using the circuit of FIG. 3.

FIG. 7 a is an exemplary model according to an embodiment of theinvention for characterizing device mismatch using the circuit of FIG.4.

FIG. 7 b is an exemplary graphical diagram illustrating subthreshold DCvoltage characteristics that were measured for a plurality of circuitsas depicted in FIG. 4.

FIG. 8 is an exemplary graphical diagram illustrating correlations ofmeasurements of neighboring pairs of transistors in a SRAM cell toverify that measured variations in device parameters, which arecharacterized using circuits and methods of the invention, are theresult of random sources.

FIG. 9 is an exemplary graphical diagram comparing the distributiondensities of Vt mismatch that are obtained using conventional models ofdopant fluctuations, with a distribution density of Vt mismatch asmeasured using circuits and methods according to the invention forcharacterizing Vt mismatch.

FIG. 10 is a flow diagram of a method for characterizing randomvariation in Vt of a semiconductor integrated circuit, according to anembodiment of the invention.

FIG. 11 is an exemplary circuit diagram of a circuit that can be usedfor characterizing device mismatch of transistors pairs of an SRAM cell,according to an embodiment of the invention.

FIG. 12 is an exemplary circuit diagram of a circuit that can be usedfor characterizing device mismatch of transistors pairs of an SRAM cell,according to another embodiment of the invention.

FIG. 13 is an exemplary circuit diagram of a circuit that can be usedfor characterizing device mismatch of transistors pairs of an SRAM cell,according to another embodiment of the invention.

FIG. 14 is an exemplary circuit diagram of a circuit that can be usedfor characterizing device mismatch of transistors pairs of an SRAM cell,according to another embodiment of the invention.

FIG. 15 is a diagram of a testing apparatus according to an embodimentof the invention for measuring device parameters for characterizingdevice mismatch.

DETAILED DESCRIPTION

In general, circuits and methods according to embodiments of theinvention are used for measuring and characterizing random variations indevice characteristics of semiconductor integrated circuit devices. Morespecifically, circuits and methods according to embodiments of theinvention enable circuit designers to accurately measure andcharacterized random variations in device characteristics (such astransistor threshold voltage (Vt)) resulting from random sources, forpurposes of integrated circuit design. Methods and circuits according toembodiments of the invention are preferably implemented for determiningvariations in Vt mismatch between neighboring MOSFETs of a given circuitbeing analyzed/designed, such as SRAM cells or other logic devices, andusing the determined variations in Vt mismatch to characterize random Vtvariation of the given circuit.

In general, circuits and methods according to the present invention forcharacterizing device mismatch preferably measure subthreshold DCvoltage characteristics (VC) of pairs of devices, which is to becontrasted with the conventional method discussed above with referenceto FIG. 1 which measures drain current I_(D) vs. gate voltage V_(G) ofindividual devices. Preferably, the DC voltage characteristic aremeasured in the sub threshold region (i.e., gate voltage is below Vt),which eliminates uncertainty that arises from unselected devices andgate leakage.

In accordance with an embodiment of the present invention, a method forcharacterizing random variations in device mismatch (e.g., Vt mismatch)between neighboring devices is performed by obtaining subthreshold DCvoltage characteristic data (Vout vs. Vin) for a plurality of devicepairs of the neighboring devices, analyzing such data to determine adistribution of Vin for a given Vout, and obtaining a distribution forVt mismatch based on the distribution of Vin. In other words, adistribution in Vt mismatch for a pair of transistors, for example, canbe directly measured using DC voltage characteristic data that isobtained from multiple pairs of such neighboring devices.

By way of example, FIGS. 2, 3 and 4 are exemplary circuit diagramsdepicting circuits that can be used for characterizing random devicemismatches (e.g., Vt mismatch) between MOSFETs. More specifically, FIG.2 is an exemplary diagram illustrating a circuit comprising a pair ofNMOS FETs, which can be used for measuring random Vt mismatches betweenNFETs. The circuit comprises a first NFET (20) having a channel width W1and length L1, and a second NFET (21) having a channel width W2 andlength L2. Further, FIG. 3 is an exemplary diagram illustrating acircuit comprising a pair of PMOS FETs, which can be used for measuringrandom Vt mismatches between PFETs. The circuit comprises a first PFET(22) having a channel width W1 and length L1, and a second PFET (23)having a channel width W2 and length L2. In addition, FIG. 4 is anexemplary diagram illustrating a circuit comprising a pair of MOSFETs,which can be used for measuring random Vt mismatches between an NFET anda PFET. The circuit comprises a PFET (24) having a channel width W1 andlength L1, and an NFET (25) having a channel width W2 and length L2.

In general, in each of the exemplary circuits, DC voltagecharacteristics are measured by sweeping an input voltage, V_(IN), andmeasuring the output voltage, V_(out). More specifically, in the circuitof FIG. 2, the input voltage V_(IN), which is applied to the gateterminal of NFET (21), and a constant voltage V_(B1) , which is appliedto the gate terminal of NFET (20) are preferably selected to maintainthe NFETS (20) and (21) in the subthreshold region for VDD>Vt. Inaddition, in the circuit of FIG. 3, the input voltage, V_(IN), which isapplied to the gate terminal of PFET (23), and a constant voltage,V_(B2), which is applied to the gate terminal of PFET (22), arepreferably selected to maintain the PFETS (22) and (23) in thesubthreshold region for VDD>Vt. Further, in the circuit of FIG. 4, theinput voltage, V_(IN), which is applied to the gate terminals of boththe PFET (24) and the NFET (25) is preferably selected to maintain theFETs (24) and (25) in the subthreshold region for VDD>Vt.

In one exemplary embodiment, the DC voltage characteristic data ismeasured in circuits of FIGS. 2-4 at VDD=to 250 mV or 1V, andmaintaining V_(B1) and V_(B2) at about less than 250 mv while varyingV_(IN) from 0v to about less than 250 mV. Advantageously, in thecircuits of FIGS. 2-4, since the input voltages are kept low to maintainthe MOSFETs in the subthreshold region, accurate characterization of Vtmismatch is achieved at full VDD, where the Vt spreads (standarddeviations) would be larger. In addition, there is no contribution fromgate leakage current and, as explained below, there is no contributionof unselected devices during testing. It is be appreciated that thephysical orientation of the MOSFETs in FIGS. 2, 3 and 4 can be in thesame direction or orthogonal.

As noted above, characterizing device mismatch (e.g., Vt mismatch)between neighboring transistors of a given circuit can be performedusing one of the circuits of FIGS. 2-4 depending on the transistortypes. For example, to characterize the variation in Vt mismatch betweentwo neighboring NFETs of a given circuit design, subthreshold DC voltagecharacteristic data (Vout vs. Vin) would be measured for each of aplurality of the same/similar circuits comprising device pairs as shownin FIG. 2. The DC data would then be analyzed to determine adistribution of Vin for a given Vout, and a distribution for Vt mismatchwould be determined using the measured distribution of Vin.

For example, FIG. 5 b is an exemplary graphical diagram illustratingsubthreshold DC voltage characteristics (Vout vs. Vin) that weremeasured for a plurality of circuits as depicted in FIG. 2. Using thedata shown in FIG. 5 b, a distribution of Vin was determined for a givenVout (as indicated by the dotted line). Preferably, Vout is selected tobe less than 0.5 VDD. More specifically, in the exemplary diagram ofFIG. 5 b, Vout is preferably selected for a region (to the right of lineA) where the transfer characteristics (Vout vs. Vout) are essentiallylinear across Vin (see dotted line). In the region of the data to theleft of line A, the DC curves (Vout vs. Vin) are not linear when Vout isselected to be higher than the Vout of the dotted line, and thenonlinear portion of the DC curves reflect contributions from othertransistors in the circuit.

Then, for the selected Vout, the distribution of Vt mismatch isdetermined using the measured distribution of Vin. More specifically, inaccordance with FIG. 5 a of the present invention, it has beendemonstrated that the distribution of Vin corresponds to thedistribution of the Vt mismatch between NFET devices. FIG. 5 a depictsan analytical model for the data plotted in FIG. 5 b. As shown in FIG. 5a, the distribution of Vin corresponds to the Vt mismatch between NFETdevices (i.e., Vt_(N2)-Vt_(N1)) of FIG. 2. In FIG. 5 a, ^(μ) denotes thesubthreshold slope factor (how quickly a device turns off as the gatevoltage decreases), ^(β) denotes the reciprocal of terminal voltage(which is 26 mv at room temperature), ^(μ) _(on) denotes the low fieldcarrier mobility, k is a coefficient (in mA/V²) that denotes the ratioof Id/(Vgs-Vt)², W/L is the ratio of channel width to channel length,and C_(ox) denotes the gate oxide capacitance.

Likewise, to characterize the variation in Vt mismatch between twoneighboring PFETs of a given circuit design, subthreshold DC voltagecharacteristic data (Vout vs. Vin) would be measured for each of aplurality of the same/similar circuits comprising device pairs as shownin FIG. 3. In this circumstance, DC transfer curves obtained would besimilar to the curves shown in FIG. 5 b for Vout vs. Vin, but the curveswould be flipped about the vertical axis, as is understood by those ofordinary skill in the art.

The DC data would then be analyzed to determine a distribution of Vinfor a given Vout, and a distribution for Vt mismatch would be determinedusing the determined distribution of Vin. In accordance with the presentinvention, it has been demonstrated that the distribution of Vincorresponds to the distribution of the Vt mismatch between PFET devices.More specifically, FIG. 6 depicts an analytical model for characterizingVt mismatch variation between neighboring PFETS, wherein it is shownthat the distribution of Vin is equal to the Vt mismatch between PFETdevices (i.e., Vt_(P2)-Vt_(P1)) of FIG. 3.

Furthermore, to characterize the variation in Vt mismatch between twoneighboring NFET and PFET transistors of a given circuit design,subthreshold DC voltage characteristic data (Vout vs. Vin) would bemeasured for each of a plurality of identical circuits comprising devicepairs as shown in FIG. 4. The DC data would then be analyzed todetermine a distribution of Vin for a given Vout, and a distribution forVt mismatch would be determined using the determined distribution ofVin.

For example, FIG. 7 b is an exemplary graphical diagram illustratingsubthreshold DC voltage characteristics (Vout vs. Vin) that weremeasured for a plurality of circuits as depicted in FIG. 4. Using thedata shown in FIG. 7 b, a distribution of Vin was determined for a givenVout (as indicated by the dotted line). Preferably, Vout is selected tobe less than 0.5 VDD. More specifically, in the exemplary diagram ofFIG. 7 b, Vout is preferably selected for a region where the transfercharacteristics (Vout vs. Vout) are essentially linear across Vin. Inthe region of the selected Vout in FIG. 7 b, the DC curves (Vout vs.Vin) are linear, but the curves become more nonlinear as Vout isincreased or decreased in relation to the dotted line.

Then, for the selected Vout, the distribution of Vt mismatch isdetermined using the measured distribution of Vin. More specifically, inaccordance with the present invention, it has been determined that thedistribution of Vin corresponds to the distribution of one-half (½) theVt mismatch between an NFET and PFET device. FIG. 7 a depicts ananalytical mismatch model for the data plotted in FIG. 7 b. As is shownin FIG. 7 a, the distribution of Vin is equal to ½ the Vt mismatchbetween the devices (i.e., (Vt_(N1)-Vt_(P1))/2) shown in FIG. 4.

FIG. 10 is a high-level flow diagram illustrating a method forcharacterizing random Vt variation of a semiconductor integrated circuitaccording to an embodiment of the invention. In general,characterization of random Vt variation of a given semiconductorintegrated circuit can be quantitatively assessed by determining arandom Vt variation for each transistor of the circuit. Preferably, todetermine the random Vt variation of the circuit transistors, the methodof FIG. 10 implements the methods described herein for characterizing Vtmismatch of transistor pairs using subthreshold DC voltagecharacteristics, wherein the distributions of Vt mismatch betweenvarious transistor pairs within the circuit are first measured, and thenused for determining the random Vt variation for each transistor in thecircuit.

A method for characterizing the random Vt variation of a semiconductorintegrated circuit according to an embodiment of the invention will nowbe described in detail with reference to FIG. 10. For purposes ofillustration, the method of FIG. 10 will be described with reference toan exemplary embodiment for characterizing random Vt variation of aconventional 6-transistor (6-T) SRAM cell. Referring to FIG. 10, apreferred characterization process begins by obtaining DC voltagecharacteristic data for various device pairs of a given circuit (step30) and then determining a distribution of Vt mismatch for each of thedevice pairs using the corresponding DC voltage characteristic data(step 31).

The DC voltage characteristic data may be obtained by retrievingpreviously measured test data that is stored in a database. Preferably,the test data is collected using various test circuits (which arepreferably similar to the desired circuit design) for measuringsubthreshold DC voltage characteristic data for different transistorpairs in the circuit.

By way of example, the exemplary device pairs illustrated in FIGS. 2, 3and 4, are commonly found in 6-transistor SRAM cells, as well as othersemiconductor integrated circuit devices that comprise NMOS and/or PMOStransistors. Accordingly, to characterize the random Vt variation of a6-T SRAM cell, various test circuits of a 6-T SRAM cell can beconstructed for measuring subthreshold DC voltage characteristics fordifferent transistor pairs in the SRAM cell and then determining the Vtmismatch distribution of neighboring transistors in the 6-T SRAM cellusing, for example, the methods described above with reference to FIGS.2-7. FIGS. 11, 12, 13 and 14 are examples of test circuits that can beused for measuring DC voltage characteristics of different transistorpairs of a conventional 6-T SRAM Cell. As explained below with referenceto FIG. 15, multiple implementations of the test circuits of FIGS. 11-14are preferably incorporated within a testing apparatus, such as theexemplary testing apparatus depicted in FIG. 15, for obtainingsufficient DC voltage characteristic data for statistical analysis.

FIG. 11 illustrates a conventional 6-T SRAM cell. The SRAM cellcomprises a pair of NMOS access transistors N1 and N2 that allow databits on bitline pair BLC, BLT to be read and written to storage nodes S1and S2, respectively. The gate terminals of access (AC) transistors N1and N2 are commonly connected to a wordline. The SRAM cell furthercomprises NMOS pull-down transistors N3 and N4, which are coupled in apositive feedback configuration with PMOS pull-up transistors P1 and P2.The operation of a 6-T SRAM cell is well-known in the art.

FIG. 11 further illustrates an exemplary test circuit that can beconstructed for measuring subthreshold DC voltage characteristics ofNMOS transistor pair N2 and N4 of the 6T SRAM cell using the methodsdescribed above with reference to FIG. 2 to determine the distributionof random Vt mismatch between the NFETs N2 and N4. More specifically,the DC voltage characteristics, Vout vs. Vin, for the transistor pairN2, N4 are preferably measured by applying a constant voltage VB1 to thegate terminal (wordline) of N2, while sweeping the input voltage, Vin,applied to the gate of N4, and measuring the output voltage, Vout, atstorage node S2. In one embodiment, the subthreshold DC voltagecharacteristics, Vout vs. Vin, for the transistor pair N2, N4 aremeasured by setting VDD to about 250 mv or lv and setting VB1 to aconstant voltage of less than about 250 mv, while sweeping Vin from 0vto a voltage that is less than about 250 mv. These DC voltagemeasurements are repeated for each of a plurality of the same testcircuits of FIG. 11, to thereby obtain a sufficient amount of data tocharacterize the transistor pair mismatch. Preferably, the data isstatistically analyzed (step 31, FIG. 10) to determine the standarddeviation of the random distribution of the Vt mismatch of transistorpair N2, N4, that is:

σ(Vt^(N4)-Vt^(N2))   (1)

It is to be appreciated that given the proximity of transistors an SRAMcell, it can be assumed that the measure (1) would be the same orsimilar with respect to the transistor pair comprising pull-down (PD)transistor N3 and access (AC) transistor N1. Therefore, for transistorpairs (N4, N2) and (N3, N1), measure (1) can be generally representedas:

σ(Vt^(PD)-Vt^(AC))   (1a)

Next, FIG. 12 illustrates an exemplary test circuit that can beconstructed for measuring subthreshold DC voltage characteristics oftransistor pair P2 and P1 of the 6T SRAM cell using the methodsdescribed above with reference to FIG. 3 to determine the random Vtmismatch distribution between the PFETs P2 and P1. More specifically,the DC voltage characteristics, Vout vs. Vin, for the transistor pairP2, P1 are preferably measured by applying a constant voltage VB2 to thegate terminal of P1, while sweeping the input voltage, Vin, applied tothe gate terminal of P2, and measuring the output voltage, Vout, at nodeS3. Furthermore, in the test circuit of FIG. 12, to accurately measurethe Vt variation of the transistor pair P2, P1 and eliminateuncertainties due to leakage currents from other transistors in thecircuit, the feedback connections between the storage nodes S1, S2 andgate terminals of storage cell transistors are removed and the gateterminals of transistors N1-N4 are grounded.

In one embodiment, the subthreshold DC voltage characteristics, Vout vs.Vin, for the transistor pair P2, P1 are measured by setting VDD to about250 mv or lv and setting VB2 to a constant voltage less than about 250mv, while sweeping Vin from 0v to a voltage that is less than about 250mv. These DC voltage measurements are repeated for each of a pluralityof the same test circuits of FIG. 12, to thereby obtain a sufficientamount of data to characterize the transistor pair mismatch. Preferably,the data is statistically analyzed (step 31, FIG. 10) to measure thestandard deviation of the random distribution of the Vt mismatch oftransistor pair P2, P1, that is:

σ(Vt^(P2)-Vt^(P1))=√{square root over (2)}·σVt^(P) ^(PU)   (2)

It is to be appreciated that since the channel length an width ofpull-up (PU) transistors P2 and P1 in an SRAM cell are the same, andgiven the proximity of such pull-up transistors an SRAM cell, it can beassumed that the standard deviation of the Vt mismatch betweentransistor pair is equal to the square root of 2 multiplied by the Vtdistribution of either device.

FIG. 13 illustrates an exemplary test circuit that can be constructedfor measuring subthreshold DC voltage characteristics of transistor pairN4 and P2 of the 6T SRAM cell using the methods described above withreference to FIG. 4 to determine the random Vt mismatch distributionbetween the transistors N4 and P2. More specifically, the DC voltagecharacteristics, Vout vs. Vin, for the transistor pair N4, P2 arepreferably measured by sweeping the input voltage, Vin, applied to thegates of N4 and P2, and measuring the output voltage, Vout, at storagenode S2. In one embodiment, the subthreshold DC voltage characteristics,Vout vs. Vin, for the transistor pair N4, P2 are measured by setting VDDto about 250 mv or lv, while sweeping Vin from 0v to a voltage that isless than about250 mv. These DC voltage measurements are repeated foreach of a plurality of the same test circuits of FIG. 13, to therebyobtain a sufficient amount of data to characterize the transistor pairmismatch. Preferably, the data is statistically analyzed (step 31, FIG.10) to measure the standard deviation of the random distribution of theVt mismatch of transistor pair N4, P2, that is:

σ(Vt^(N4)-Vt^(P) ²)   (3)

It is to be appreciated that given the proximity of transistors an SRAMcell, the measure (3) would be the same or similar with respect topull-down (PD) transistor N3 and pull-up (PU) transistor P1. Therefore,for transistor pairs (N4, P2) and (N3, P1), measure (3) can be generallyrepresented as:

σ(Vt^(PD)-vT^(PU))   (3a)

FIG. 14 illustrates an exemplary test circuit that can be constructedfor measuring subthreshold DC voltage characteristics of transistor pairN3 and N4 of the 6T SRAM cell using the methods described above withreference to FIG. 2 to determine the random Vt mismatch distributionbetween the NFETs N3 and N4. More specifically, the DC voltagecharacteristics, Vout vs. Vin, for the transistor pair N3, N4 arepreferably measured by applying a constant voltage VB1 to the gateterminal of N3, while sweeping the input voltage, Vin, applied to thegate of N4, and measuring the output voltage, Vout, at node S4. In oneembodiment, the subthreshold DC voltage characteristics, Vout vs. Vin,for the transistor pair N3, N4 are measured by setting VDD to about 250mv or lv and setting VB1 to a constant voltage less than about 250 mv,while sweeping Vin from 0v to a voltage that is less than about 250 mv.These DC voltage measurements are repeated for each of a plurality ofthe same test circuits of FIG. 14, to thereby obtain a sufficient amountof data to characterize the transistor pair mismatch. Preferably, thedata is statistically analyzed (step 31, FIG. 10) to measure thestandard deviation of the random distribution of the Vt mismatch oftransistor pair N4, N3, that is:

σ(Vt^(NA)-Vt^(N3))=√{square root over (2)}·σVt^(N) ^(PD)   (4)

It is to be appreciated that since the channel length an width ofpull-down (PD) transistors N4 and N3 in an SRAM cell are designed to bethe same, and given the proximity of such pull-down transistors an SRAMcell, it can be assumed that the standard deviation of the Vt mismatchbetween transistor pair is equal to the square root of 2 multiplied bythe Vt distribution of either device.

Referring again to FIG. 10, once the random distributions of Vt mismatchfor the desired device pairs are determined (step 31), the measured Vtmismatch distributions are preferably used for determining the random Vtvariation for each of the devices in the circuit (step 32). Forinstance, in the exemplary embodiment of an SRAM cell as describedabove, measures (1a) and (4) are used for determining σVt^(AC), measure(2) yields σVt^(PU), and measure (4) yields σVt^(PD), for the exemplaryvoltages noted above. Measures 3a and 4 can also yield σVt^(PU).

The measured Vt variations can then be used to quantitativelyassess/characterize the overall random Vt variation of the circuits anddetermine the affects of such random Vt variation on circuit performance(step 33).

It is to be understood that the methods described herein for collectingand statistically analyzing subthreshold DC voltage data may beimplemented in various forms of hardware, software, firmware, specialpurpose processors, or a combination thereof. For instance, the methodof FIG. 10 may be implemented as an application comprising programinstructions that are tangibly embodied on one or more program storagedevices (e.g., hard disk, magnetic floppy disk, RAM, ROM, CD ROM, etc.)and executable by any device or machine comprising suitablearchitecture.

FIG. 15 is an exemplary diagram illustrating a testing apparatusaccording to an embodiment of the present invention, which can be usedfor measuring DC voltage characteristic data for test circuits. FIG. 15a illustrates an exemplary testing apparatus (40) comprising a pluralityof cell columns (C1, C2, . . . C1) and a plurality of correspondingmultiplexers (M1, M2, . . . Mi). Each cell column Ci comprises aplurality of test circuits (1, 2, . . . , 2 ^(N)) that are constructedfor measuring test data. For example, each test circuit in a givencolumn Ci could correspond to any of the circuits depicted in FIGS. 2-4or FIGS. 11-14. Each column Ci is identical with respect to itsconstituent test circuits, e.g., test circuit 1 in each column Ci is thesame, and so on.

Preferably, each column Ci is designed to include a variety of circuitsthat would provide sufficient test data to effectively characterize thecircuits) under considerations. For instance, each cell column maycomprise multiple configurations of the circuits shown in FIGS. 2-4 withvariations in channel widths W1, W2, channels lengths L1, L2 andorientation of the device pairs. Furthermore, for measuring DC voltagecharacteristic data for a 6T SRAM cell as discussed above, each cellcolumn (Ci) may include multiple configuration of the circuits shown inFIGS. 11-14. For example, assume that N=8 and, thus, there are 1024cells in each column. Then, in each column Ci, the first 256 cells maycomprise the test circuit depicted in FIG. 11, the next 256 cells maycomprise the test circuit depicted in FIG. 12, the next 256 cells maycomprise the test circuit depicted in FIG. 13, and the last 256 cellsmay comprise the test circuit depicted in FIG. 14.

FIG. 15 b illustrates one of the cell columns (e.g., C1) andcorresponding multiplexer (e.g., M1) in the testing apparatus (40),although it is understood that all cell columns are identical instructure. As shown in FIG. 15( b), a Vin terminal of the testingapparatus (40) is commonly connected to Vin terminals of each testcircuit in the column C1 (as well as the other columns across thetesting apparatus). During operation, the multiplexer M1 selects one ofthe 2^(N) cell Vouts with N address bits using CMOS pass gates of theMultiplexer M1. More specifically, Vout measurements are simultaneouslyobtained for each corresponding cell in all cell columns across thetesting apparatus. Furthermore, a mechanism is provided for applying Vinto only those circuits whose outputs are being selected by themultiplexer. In one embodiment, a decoder that selects a pass-gate inthe multiplexer enables only the selected cell corresponding to thepass-gate to be measured. Thus, the multiplexers comprise decoders andpass-gates.

It is to be appreciated that the testing apparatus (40) can be operatedunder the control of computer or any control system as is known in theart, which can generate control signals (e.g., address bits N) andmeasure and collect test data that is output from the testing apparatus.

Preferably, the transistors (CMOS pass gates) of the multiplexer M1 areconstructed to have long and wide device widths, which significantlyreduces/eliminates the uncertainty that could be added to the measuredvoltage characteristics as a result of leakage currents from the Muxtransistors. In addition, the multiplexer M1 preferably operates with alow VDD1 and RBB (reverse body bias) to further reduce the uncertaintythat could be added to the measured voltage characteristics. Moreover,the value N can be selected based on the leakage uncertainty from theMux transistors to Vout.

To verify that the measurements shown in FIGS. 5 b and 7 b, for example,were the result of random sources and not systematic (manufacturing)sources, the Vt mismatch for the right side of an SRAM cell was comparedwith the Vt mismatch for the left side of the SRAM cell and the data wasplotted. FIG. 8 is an exemplary graphical diagram illustratingcorrelations of measurements of neighboring pairs of transistors in aSRAM cell to verify that measured variations in device parameters, whichare characterized using circuits and methods of the invention, are theresult of random sources. If the variation was due to systematicsources, there would be spatial correlation. For instance, the measuredVin as shown in FIG. 5 b or 7 b for each characteristic would move inthe same direction for the left or right side of the cell, due tospatial correlation of systematic sources of variation , i.e., themismatch of two neighboring devices would move in the same direction dueto systematic sources of variation. However, as shown in FIG. 8, thecorrelation coefficients were determined to be less than 0.05, whichindicates a marginal correlation between data measurements between theright and left side of the cell (i.e., the variations are overwhelminglyrandom).

FIG. 9 is an exemplary graphical diagram comparing the distributiondensities of Vt mismatch that were obtained using conventional models ofdopant fluctuations, with a distribution density of Vt mismatch asmeasured using circuits and methods according to the invention forcharacterizing Vt mismatch. In particular, FIG. 9 depicts the measureddistribution of Vt mismatch that was obtained using the data shown inFIGS. 5 b and 7 b as compared with analytical models for Vt variationsthat are obtained from dopant fluctuations. As shown in FIG. 9, themeasured distribution is similar to the distributions determined fromthe analytical models. Thus, it can reasonably be concluded that thecircuits and methods described herein in accordance with the presentinvention effectively measure random sources of variation due to dopantfluctuations, which is a primary source for random Vt variation inneighboring devices.

Although exemplary embodiments have been described herein with referenceto the accompanying drawings, it is to be understood that the presentsystem and method is not limited to those precise embodiments, and thatvarious other changes and modifications may be affected therein by oneskilled in the art without departing from the scope or spirit of theinvention. All such changes and modifications are intended to beincluded within the scope of the invention as defined by the appendedclaims.

1. A testing apparatus for characterizing device mismatch in asemiconductor integrated circuit, comprising: a plurality of testcircuits, wherein each test circuit is configured for obtainingsubthreshold DC voltage characteristic data for a device pair of anintegrated circuit; and a multiplexer, for selectively outputting anoutput voltage from each test circuits.
 2. The testing apparatus ofclaim 1, wherein a portion of the plurality of test circuits areconfigured for testing the same device pair.
 3. The testing apparatus ofclaim 1, wherein the plurality of test circuits are divided into groupsof test circuits, wherein each group of the test circuits comprises thesame test circuits.
 4. The testing apparatus of claim 1, wherein eachgroup of test circuits is associated with a multiplexer, wherein themultiplexers are controlled such that the output voltages from similartest circuits in each group are simultaneously measured.
 5. The testingapparatus of claim 1, further comprising a database for storing thesubthreshold DC voltage characteristic data.
 6. The testing apparatus ofclaim 5, further comprising a processing unit for statisticallyprocessing the subthreshold DC voltage characteristic data stored indatabase for determining a distribution of device mismatch of theintegrated circuit.
 7. A testing apparatus for characterizing devicemismatch in a semiconductor integrated circuit, comprising: a pluralityof test circuits, wherein each test circuit is configured for obtainingsubthreshold DC voltage characteristic data for a device pair of anintegrated circuit, the device pair selected by a test circuit of theplurality of test circuits corresponding to the device pair, wherein thedevice pair comprise neighboring first and second transistors, whereinthe subthreshold DC voltage characteristic data for the selected devicepair comprises an output DC voltage V_(ouT) as a function of an input DCvoltage V_(IN), wherein V_(IN) is applied to a gate of at least one ofthe first and second transistors and wherein V_(ouT) is obtained at acommon node connection of the first and second transistors, and whereinthe DC voltage characteristic data is obtained with the first and secondtransistor devices operating in a subthreshold region; and amultiplexer, for selectively outputting an output voltage from each testcircuits.
 8. The testing apparatus of claim 7, wherein at least two ofthe plurality of test circuits are configured for testing the devicepair.
 9. The testing apparatus of claim 7, wherein the plurality of testcircuits are divided into groups of test circuits, wherein each group ofthe test circuits comprises a same type of test circuit.
 10. The testingapparatus of claim 9, wherein each group of test circuits is associatedwith a different multiplexer, wherein the multiplexers are controlledsuch that the output voltages from the same type test circuits in eachgroup are simultaneously measured.
 11. The testing apparatus of claim 9,further comprising a database for storing the subthreshold DC voltagecharacteristic data.
 12. The testing apparatus of claim 12, furthercomprising a processing unit for statistically processing thesubthreshold DC voltage characteristic data stored in database fordetermining a distribution of device mismatch of the integrated circuit.13. A test circuit comprising: a pair of access transistors; a bitlinepair comprising a first bitline and a second bitline connected torespective transistors of the pair of access transistors, respectively;a pair of storage nodes connected to respective transistors of the pairof access transistors; a wordline commonly connected to gate terminalsof the pair of access transistors; and a pair of pull-down transistorscoupled with a pair of pull-up transistors, wherein each storage node ofthe pair of storage nodes is disposed between a respective pull-downtransistor and a respective pull-up transistor.
 14. The test circuit ofclaim 13, wherein gates of the pair of pull-down transistors areconnected to a ground voltage.
 15. The test circuit of claim 13, whereingates of the pair of access transistors are connected to a groundvoltage.
 16. The test circuit of claim 13, wherein gates of the pair ofaccess transistors are connected to a constant voltage.
 17. The testcircuit of claim 13, wherein a first storage node of the pair of storagenodes is connected to a gate terminal of a first pull-down transistor ofthe pair of pull-down transistors and connected to a drain terminal of asecond pull-down transistor of the pair of pull-down transistors, and asecond storage node of the pair of storage nodes is connected to a gateterminal of a second pull-down transistor of the pair of pull-downtransistors and connected to a drain terminal of a first pull-downtransistor of the pair of pull-down transistors.
 18. The test circuit ofclaim 13, wherein a first storage node of the pair of storage nodes isconnected to a gate terminal of a first pull-up transistor of the pairof pull-down transistors and connected to a source terminal of a secondpull-up transistor of the pair of pull-up transistors, and a secondstorage node of the pair of storage nodes is connected to a gateterminal of a second pull-up transistor of the pair of pull-downtransistors and connected to a drain terminal of a first pull-uptransistor of the pair of pull-up transistors.